Breaking complex chips into smaller pieces allows for much more customization, particularly for domain-specific applications, ...

New connectivity standard brings performance improvements and a bunch of new features, but it may take years before they are ...

Configurability causes an explosion in verification complexity, but the upside is verification engineers are gaining in ...

Predictions should not reflect innovation or breakthroughs. They should be based on pain. At this point everyone has made ...

Avoid power leaks, power-ground DC paths, and missing level shifters with symbolic simulation. Nothing is worse for a design ...

As integrated circuit (IC) designs grow in complexity, traditional design rule checking (DRC) methods struggle to keep pace. Originally developed for simpler, custom layouts, traditional DRC uses an ...

The increasing complexity of integrated circuit (IC) designs is straining our traditional design rule checking (DRC) methods. The iterative “construct by correction” approach that worked well for ...

Scalable Low-Cost CXL Memory Pooling” was published by researchers at University of Washington, Microsoft Azure and Columbia ...

A new technical paper titled “Controlling Speckle Contrast Using Existing Lithographic Scanner Knobs to Explore the Impact on ...

Two technical papers were published by researchers at Georgia Tech and Ruhr University Bochum detailing CPU side-channel attack vulnerabilities on Apple devices that could reveal confidential data.

A chiplet supermarket is still years off, but progress is being made on all fronts.

A new technical paper titled “Ultranarrow Semiconductor WS2 Nanoribbon Field-Effect Transistors” was published by researchers at Chalmers University of Technology. Abstract “Semiconducting transition ...